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18.7. LEUART - NRZ vs. RZI ......................................................................................................................
19.1. TIMER Block Overview .......................................................................................................................
19.2. TIMER Hardware Timer/Counter Control ................................................................................................
19.3. TIMER Clock Selection .......................................................................................................................
19.4. TIMER Connections ...........................................................................................................................
19.5. TIMER TOP Value Update Functionality .................................................................................................
19.6. TIMER Quadrature Encoded Inputs .......................................................................................................
19.7. TIMER Quadrature Decoder Configuration ..............................................................................................
19.8. TIMER X2 Decoding Mode ..................................................................................................................
19.9. TIMER X4 Decoding Mode ..................................................................................................................
19.10. TIMER Input Pin Logic ......................................................................................................................
19.11. TIMER Input Capture Buffer Functionality .............................................................................................
19.12. TIMER Output Compare/PWM Buffer Functionality .................................................................................
19.13. TIMER Input Capture ........................................................................................................................
19.14. TIMER Period and/or Pulse width Capture ............................................................................................
19.15. TIMER Block Diagram Showing Comparison Functionality ........................................................................
19.16. TIMER Output Logic .........................................................................................................................
19.17. TIMER Up-count Frequency Generation ...............................................................................................
19.18. TIMER Up-count PWM Generation ......................................................................................................
19.19. TIMER Up/Down-count PWM Generation ..............................................................................................
19.20. TIMER Dead-Time Insertion Unit Overview ...........................................................................................
19.21. TIMER Triple Half-Bridge ...................................................................................................................
19.22. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel ..................................................
19.23. TIMER Polarity of Both Signals are Set as Active-High ............................................................................
19.24. TIMER Output Polarities ....................................................................................................................
20.1. RTC Overview ...................................................................................................................................
21.1. LETIMER Overview ............................................................................................................................
21.2. LETIMER State Machine for Free-running Mode ......................................................................................
21.3. LETIMER One-shot Repeat State Machine .............................................................................................
21.4. LETIMER Buffered Repeat State Machine ..............................................................................................
21.5. LETIMER Double Repeat State Machine ................................................................................................
21.6. LETIMER Simple Waveforms Output .....................................................................................................
21.7. LETIMER Repeated Counting ..............................................................................................................
21.8. LETIMER Dual Output ........................................................................................................................
21.9. LETIMER Triggered Operation .............................................................................................................
21.10. LETIMER Continuous Operation .........................................................................................................
21.11. LETIMER LETIMERn_CNT Not Initialized to 0 .......................................................................................
22.1. PCNT Overview .................................................................................................................................
22.2. PCNT Quadrature Coding ...................................................................................................................
22.3. PCNT Direction Change Interrupt (DIRCNG) Generation ...........................................................................
23.1. ACMP Overview ................................................................................................................................
23.2. 20 mV Hysteresis Selected ..................................................................................................................
23.3. Capacitive Sensing Set-up ...................................................................................................................
24.1. VCMP Overview ................................................................................................................................
24.2. VCMP 20 mV Hysteresis Enabled .........................................................................................................
25.1. ADC Overview ..................................................................................................................................
25.2. ADC Conversion Timing ......................................................................................................................
25.3. ADC Analog Power Consumption With Different WARMUPMODE Settings ....................................................
25.4. ADC RC Input Filter Configuration ........................................................................................................
25.5. ADC Bias Programming ......................................................................................................................
25.6. ADC Conversion Tailgating ..................................................................................................................
26.1. DAC Overview ..................................................................................................................................
26.2. DAC Bias Programming ......................................................................................................................
26.3. DAC Sine Mode ................................................................................................................................
27.1. AES Key and Data Definitions ..............................................................................................................
27.2. AES Data and Key Orientation as Defined in the Advanced Encryption Standard ............................................
27.3. AES Data and Key Register Operation ..................................................................................................
28.1. Pin Configuration ...............................................................................................................................
28.2. Tristated Output with Optional Pull-up or Pull-down ..................................................................................
28.3. Push-Pull Configuration .......................................................................................................................
28.4. Open-drain .......................................................................................................................................
28.5. Pin n Interrupt Generation ...................................................................................................................
29.1. LCD Block Diagram ...........................................................................................................................
29.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ........................................
29.3. LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias ............................................
29.4. LCD Static Bias and Multiplexing - LCD_COM0 .......................................................................................
29.5. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM0 ................................................................................
29.6. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM1 ................................................................................
29.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 .................................................................................
29.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection .................................................................
29.9. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 ................................................................
29.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 ..............................................................
29.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0 ..............................................................................
29.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 ..............................................................................
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2011-04-12 - d0001_Rev1.10
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